Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The radiation can be light, such as ultra-violet light, vacuum ultra-violet (VUV) light and deep ultraviolet light. The radiation can also be x-ray radiation, e-beam radiation, etc.
The lithographic photoresist coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the lithographic coating through a photomask or reticle causes the image area to become selectively either more or less soluble (depending on the negative or positive photoresist coating) in a particular developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The photoresist material or layer associated with conventional lithographic technologies is often utilized to selectively form various IC structures, regions, and layers. Generally, the patterned photoresist material can be utilized to define doping regions, implant regions or other structures associated with an integrated circuit (IC). A conventional lithographic system is often utilized to pattern photoresist material to form gate stacks or structures. As the features in semiconductor patterning become smaller and smaller, the photoresist thickness needed to sustain reasonable aspect ratio must decrease. A thinner photoresist may not be suitable for etch applications due to premature resist erosion. Thus, resist erosion complications facilitate the necessity for hard mask processes.
According to one conventional process, a hard mask is provided above polysilicon/oxide layers to pattern the gate stacks. The hard mask must be thin enough so that it can be etched without eroding the patterned photoresist above it. The hard mask must also be thick enough to withstand an etch process so that uncovered portions of the underlying layer (e.g., polysilicon layer) can be completely removed. Accordingly, the hard mask must have a precise thickness to appropriately pattern the gate stacks.
An anti-reflective coating (ARC) has been conventionally provided underneath the photoresist material or the hard mask to reduce reflectivity and thereby, reduce resist notching, lifting and variation of critical dimension of the obtained pattern. Generally, the ARC (organic or inorganic) is a relatively thin layer which cannot be used as a hard mask because it is too thin and does not allow thickness flexibility due to optical design parameters.
Advanced lithography is utilizing higher numerical apertures (NA) to achieve smaller feature sizes. However, the use of higher NA affects the reflectivity of the ARC. The effects on reflectivity associated with higher NAs makes designing a optimal thicknesses for an ARC more difficult. For example, reflectivity requirements due to the use of higher NA's and thickness requirements for bottom anti-reflective coatings (BARCs) are not coincident.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need for a process of forming a gate stack that does not require a conventional hard mask step. Yet further, there is a need for a hard mask that has low reflectivity at high NA. Even further still, there is a need for a gate mask process that effectively balances optical and etching efficiencies, especially at ultra high NA. Yet even further still, there is a need for a dual layer hard mask that has less than 1% reflectivity at high NAs and can be used with dual poly flow processes.